高精度多环片自动装配控制技术

为了实现对微小环片零件的自动化装配,搭建了自动装配系统.通过4根直线导向轴与4个直线轴承来提高系统的导向精度和刚度.采用直线导轨进行各装配作业模块之间的切换,保证了微小环片零件的自动装配与取出.在环片的装配方向上,螺旋升降机和光栅尺实现环片的位置精度控制.在Lab VIEW编程环境中,采用分层软件架构和模块化控制思想,避免了不必要的数据循环检测与丢失,能够达到环片组件的装配精度要求.控制系统分为系统初始化模块、参数设置模块、装配模块和取出模块,自动装配系统通过各个模块间的相互交流配合完成装配任务.采用本文中自动装配系统装配环片的实验结果表明,环片零件装配的最大位置误差为26μm,垂直度误差为17μm,平均装配时间为75 s/片,可满足环片组件所需的精度要求.     

基于振动实测的非均质地层钻头失效分析与对策

四川盆地作为国内页岩气开发的重点区域,通过近几年的不断攻关和实践,机械钻速得到了提高,但由于受地层复杂、可钻性差、非均质性强等地质因素的影响,导致井下钻柱系统不良振动剧烈,容易出现钻头损坏严重、钻速较低等问题,严重影响了钻井时效。为了解决上述难题,以该盆地涪陵工区上二叠统龙潭组—中二叠统茅口组为例,采用井下振动高频测量工具的实测手段,测量了钻头—钻柱系统的动态振动加速度参数,结合地层的岩性和矿物组分分析,研究钻头失效原因与对策,并开展了现场试验。研究结果表明:①在非均质地层中钻进的钻头—钻柱系统产生了大于40 m/s~2的高幅值瞬时冲击振动,高幅值的瞬时冲击是导致钻头先期失效的主要原因;②提出了抑制高幅值的瞬时冲击振动采用"减振+增压"工具组合和避免井下工具共振的钻井参数;③采用钻井新参数的试验井比邻井的高幅值瞬时振动降低了17%,单只钻头进尺增加24%,钻头工作环境得到了较大的改善,钻头使用数量减少。结论认为,该研究成果能够有效地改善钻头—钻柱系统的振动状态,有利于达成延长钻头使用寿命的目标。     

Durable,Sensitive, and Wide‐Range Wearable Pressure Sensors Based on Wavy‐Structured Flexible Conductive Composite Film

Flexible pressure sensors have potential applications in human motion monitoring and electronic skins. To satisfy the practical applications, pressure sensors with a high sensitivity, a low detection limit, a broad response range, and an excellent stability are highly needed. Here, a piezoresistive pressure sensor based on wavy‐structured single‐walled carbon nanotube/graphite flake/thermoplastic polyurethane (SWCNT/GF/TPU) composite film is fabricated by a prestretching process. Due to the random wavy structure, high conductivity, and good flexibility, the prepared sensor displays a low detection limit of 2 Pa, a wide sensing range of 0–60 kPa, and a high sensitivity of 5.49 kPa^?1 for 0–50 Pa. Furthermore, the sensor shows a remarkable repeatability of over 1.1 × 10⁴, 9.0 × 10³, and 2.0 × 10³ pressure loading/unloading cycles at 50 Pa, 500 Pa, and 30 kPa, respectively, and a fast responsibility of 100–150 ms of loading response time and 400–600 ms of relaxation time. Therefore, the pressure sensor is successfully adopted to monitor both the large‐scale human activities (e.g., walk and jump) and the small‐scale signals (e.g., wrist pulse). Furthermore, a sensor array is assembled to map the weight and shape of an object, indicating its various potential applications including human–machine interactions, human health monitoring, and other wearable electronics.     

一种军棋机器博弈的多棋子协同博弈方法

针对在军棋博弈不完全信息对弈中，面对棋子不同价值、不同位置、不同搭配所产生的不同棋力，传统的单子意图搜索算法，不能满足棋子之间的协同性与沟通性，同时也缺乏对敌方的引诱与欺骗等高级对抗能力。本文提出一种结合UCT搜索策略的高价值棋子博弈方法，实现高价值棋子协同博弈的策略。实战经验表明:高价值多棋子军棋协同博弈策略优于单棋子军棋博弈策略。     

冷轧退火对FeMnCoCrAl高熵合金组织和力学性能的影响

使用真空电弧炉熔炼出(Fe₅₀Mn₃₀Co₁₀Cr₁₀)₉₄Al₆合金,利用冷轧及在不同温度对合金进行退火,以期望得到由多尺度再结晶晶粒构成的层状结构;并对不同退火温度的样品进行拉伸性能测试。利用扫描电镜和EBSD对合金组织形貌进行表征,采用X射线衍射方法研究其相组成。结果表明:合金在铸态和冷轧后相组成未发生变化,700 ℃退火得到较好的多尺度再结晶晶粒的层状结构,其屈服强度为487 MPa,抗拉强度为708 MPa,断后伸长率为39%,表现出良好的综合力学性能。     

基于ＰＩＤ控制算法的直流微网容错控制方法研究

构建直流微网容错控制对象模型，调节直流微电网的输出回路参数；以输出功率、直流微网的 参考电压、弱电网下系统惯性响应特征等为约束参量，构建直流微网容错控制目标函数，在不同电网强度下 进行直流微网容错控制的参数自整定性调节，采用无功环比例积分控制方法进行直流微网容错寻优分析， 建立模糊 ＰＩＤ控制模型，采用变结构的模糊 ＰＩＤ控制方法进行直流微网容错控制过程中的自适应加权学习 和误差反馈调节，实现直流微网容错控制改进设计。仿真结果表明，采用该方法进行直流微网控制的容错 性能较好，输出稳定性较强，具有较好的直流微网输出增益。     

电子行业用高纯钯的制备研究

高纯钯在电子行业等领域应用广泛，需求迫切。以氯化钯为原料，提出采用氯化铵沉淀-氨水配合联合工艺净化钯溶液，水合肼还原纯净钯溶液制备高纯钯。结果表明，固体氯化钯溶解后，在合适的条件下，该钯溶液经过氧化-氯化铵沉淀、氨水配合有效去除杂质元素，获得纯净二氯四氨合钯溶液，再经水合肼还原后，获得纯度99.999%高纯钯，其碳、氧、氮等杂质元素总含量小于355×10^-6。     

High-Tg porous polyimide films with low dielectric constant derived from spiro-(adamantane-2,9′(2′,7′-diamino)-fluorene)

Porous polyimide (PI) films with low dielectric constants and excellent thermal properties have been a pressing demand for the next generation of high-performance, miniature, and ultrathin microelectronic devices. A series of novel porous PI films containing fluorenyl-adamantane groups were prepared successfully via thermolysis of poly(ethylene glycol) (PEG) added in the PI matrix. The cross-sectional morphologies of porous PI films showed closed pores with diameters ranging from 135 to 158 nm, which were uniform and regular in shape without interconnectivity. These porous PI films exhibited excellent thermal properties with a glass-transition temperature at 376 °C whereas the 5% weight loss temperature in air excess of 405 °C due to enhanced rigidity afforded by fluorenyl-adamantane groups. Accompanied by thermolysis content of PEG increasing from 0 to 20 wt %, the density of porous PI films decreased, and the corresponding porosity grew significantly from 0 to 11.48%. Depending on porosity, the dielectric constant and dielectric loss of porous PI films significantly declined from 2.89 to 2.37 and from 0.050 to 0.021, respectively. These excellent properties benefit the as-prepared porous PI films for application as interlayer dielectrics, integrated circuit chips, or multichip modules in microelectronic fields. © 2018 Wiley Periodicals, Inc. J. Appl. Polym. Sci. 2019 , 136, 47313.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.